ASIC DESIGN: Added Power and Grounds

2007 Story Set

October 16, 2007
In the early (1980s) ASIC design era, newly launched, pre-Design Compiler, pre-Standardized netlists, pre-RTL, designers were faced with:
* Complete customized multi-layer chip/wafer design. This was prohibitively expensive at that time, unless you were designing for space or defense or had a big R&D budget.
* Standardized sizes of arrays (per product line) in which you picked the die size (core and I/O) that best fit your design.
This led to I/O limited (you ran out of pads) or core-limited (too-high utilization in the days of routing channels led to placement and routing headaches and often failure)
Today, we can build any die size we want, but we are faced with very real cost limitations and package cavity sizing issues (which remain as they were). Bonding becomes a critical design consideration.
We still have the need to examine the I/O of a design to determine how many added power and grounds, those I/O pins that must be used for power and ground beyond what is supplied on the basic die layout.
Power and ground are in the corners on most die, and often also in the middle of the sides of larger die.
It is not enough. Certain conditions require that you add more.
What are those conditions? The same ones that we handled in the 1980s. The technology changed, but the basic design rules did not. If anything, today's tighter tolerances and smaller process technologies (read Deep Submicron) made things worse.
1. Signal isolation: high-speed and other sensitive signals need to be protected from certain other signals, most notably data busses, and need to be isolated so that they do not disturb their neighbors.
2. Simultaneous switching Outputs (SSOs) in which a gang of signals all try to switch at the same instant of time. They don't actually make it to the precise instant, but they get close enough. They "pull" on the power bus and disturb their neighbors.
3. Critical signals that could themselves be disturbed must be protected.
4. IP module requirements - and today's ASICs are 70-90% IP blocks. Some of them have specific requirements on layout and placement.
We have memory on-board now, with its requirements on speed and access. ROM, RAM, and PROM to start with are heavily populated and push die sizes larger. How much memory is needed?
Bus width is another decision as wide busses mean speed; narrow busses require a faster clock. The faster the clock, the more power and often an increased need for isolation of the clock signal. (One hand give-ith and one hand take-ith away.)
Die size, packaging requirements push back on the number of I/O and added power and ground.
For commercial products, Marketing strongly drives the desired speed, the package (based on the target product), and other performance requirements. All of these push on the designer.
Then, there is consideration of the layout demands.
For products, quite often all four sides of a die are not used for bonding. When only 1 or 2 sides of a die are to be allocated for I/O, this increases the pressure on the existing die pads. Sometimes pads have multiplexed signals feeding to them to cut down on external connections.
Another issue is the dimensions of the die pad. Sometimes the bonding (in the corners for example) is such that the pad must be strapped together and two serve as one. This is done for high-current signals and also when a pad becomes useless because it cannot be probed or bonded out on its own. This puts pressure on the other die pads to handle the pin count load. (Yes, we have shrunk so small that the test technology is still struggling to play catch up. By the time they do, we will have jumped even smaller.)
No matter what, you have to have the calculated added power and ground. You cannot delete them to "fit".
And we didn't mention the added test pads (JTAG and others).
And we would love to build the product with a spare pad (to go along with spare guts).

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