Everything Old is New Again---

Dec, 2008

Looking at old seminars that I wrote and taught a decade or two ago is a very interesting adventure, especially since they are back-engineering the AMCC 20000 and Bit-Slice is in RTL soft IPs and in many new designs today. My books are still on-line and I still get email. (They must be good. Google is trying to steal them.)

I taught, at the basis, design flow methodology and structured design.

These principles are still what we must use today if we are to design for first-time design success. Skipping design flow steps will cost you, perhaps not the first time, but eventually. Cost-cutting by skipping the inexpensive early-stage testing and analysis, and lumping it at the end of the design flow, where it is more complex and more expensive, can and does result in "show stoppers", where the design leaves the wafer fab schedule and faces long TTM (time to market) delays. I have seen projects die before birth, or die in the prototype lab. It always comes down to steps skipped and overlooked. (The computer prototype that took out the subpower station in Pasadena one afternoon will always be fondly remembered. Yes - that project was canceled.)

The old adage, "Those who do not study history are bound to repeat it" applies.

By understaiding how we got to the point at which we find ourselves, and by understanding the theory behind what the EDA software tools are doing, we can better handle today's design task.

The other point of interest, I went on to teach five years at Synopsys (1997-2002), using the tools that did not exist when we did the earlier designs. The design flow is the same. (I was the lead developer for the Advanced Chip Synthesis class and the Project Manager for the eLearning conversion of that seminar.)

The tools changed, the ease of doing the steps changed, the details changed, but the design flow remained. Understanding both the logic design and the physical design is something most engineers lack. They know one or the other. Designs have become that complicated.

Not really. It is the very same flow we had in the 70s, 80s, 90s. The technology (bipolar, BiCOMS, CBA, CMOS) is actually irrelevant. Hand-placing macros on a field of cells, using cell-based arrays, or sea-of-cells, only affects the details. Whether you have 2-layer metalization 3 inch wafers or 6 layer 12 inch wafers, or the proposed 18-inch wafer and my head hurts at how many metal layers, routing channels or routing-free sea-of-cells makes little difference. The overall flow? Unchanged.

I wrote and taught seminars for the cell-based arrays up until there was a technical breakthrough, and CMOS designs all of a sudden could build smaller dies than the CBA ones. That event changed ASIC from mostly CBA to mostly CMOS almost overnight (around 1999).

Today we don't swoon over a 700-gate ASIC, we have designs in the millions of gates. FPGA has come up to the 4 million mark and taken away more of the ASIC business. And we just keep evolving.

But that basic design flow, the concept of correct by design, and structured design, these things remain. If you are smart enough to use them.

Otherwise, keep your resume updated.